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PI74SSTUA32864
25-Bit 1:1 or 14-Bit 1:2 Configurable Registered Buffer
Features
Designed for low-voltage operation: VDD = 1.8V Supports Low Power Standby Operation Enhanced Signal Integrity for 1 and 2 Rank Modules All Inputs are SSTL_18 compatible, except RST, C0, C1, which are LVCMOS. * Output drivers are optimized to drive DDR2 DIMM loads * Packaging (Pb-free & Green available): 96-Ball LFBGA (NB) * Used in DDR2-400/533/667 memory applications * * * *
Description
Pericom Semiconductor's PI74SSTUA32864 is a 25-Bit 1:1 or 14-Bit 1:2 configurable registered buffer and designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V drivers that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18 specifications. The device operates from a differential clock (CK and CK). Data is registered at the crossing of CK going high, and CK going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration for 25-Bit 1:1 (when LOW) to 14-Bit 1:2 (when HIGH). The device supports low-power standby operation. When the reset input (RST) is low, the differential input receivers are disabled and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition , when RST is low, all registers are reset, and all outputs are forced low. The LVCMOS RST and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RST must be held in the low state during power up. In the DDR2 RDIMM application, RST is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST until the input receivers are fully enabled, the design of the registered buffer must ensure that the outputs remain low, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs will function normally. The RST input has priority over the DCS and CSR control will force the outputs low. If the DCS control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the set-up time requirement for DCS would be the same as for the other D data inputs.
Block Diagram 1:2 Mode (Positive Logic)
RST
CK CK
VREF
DCKE
1D C1 R
QCKEA
QCKEB* QODTA
DODT
1D C1 R
QODTB*
DCS 1D C1 R
QCSA
QCSB*
CSR
D1
0 1 1D C1 R Q1B* Q1A
Note: Disabled in 1:1 configuration TO OTHER CHANNELS
07-0266
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PS8743D
11/06/07
PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer
Pin Configuration 1:1 Register (C0 = 0, C1 = 0)
1 A B C D E F G H J K L M N P R T DCKE D2 D3 DODT D5 D6 NC CK CK D8 D9 D10 D11 D12 D13 D14 2 NC D15 D16 NC D17 D18 RST DCS CSR D19 D20 D21 D22 D23 D24 D25 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 5 QCKE Q2 Q3 QODT Q5 Q6 C1 QCS ZOH Q8 Q9 Q10 Q11 Q12 Q13 Q14 6 NC Q15 Q16 NC Q17 Q18 C0 NC ZOL Q19 Q20 Q21 Q22 Q23 Q24 Q25
Pin Configuration 1:2 Register (C0 = 0, C1 = 1)
1 A B C D E F G H J K L M N P R T DCKE D2 D3 DODT D5 D6 NC CK CK D8 D9 D10 D11 D12 D13 D14 2 NC NC NC NC NC NC RST DCS CSR NC NC NC NC NC NC NC 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 5 Q2A Q3A Q5A Q6A C1 QCSA ZOH Q8A Q9A Q10A Q11A Q12A Q13A Q14A 6 Q2B Q3B Q5B Q6B C0 QCSB ZOL Q8B Q9B Q10B Q11B Q12B Q13B Q14B QCKEA QCKEB
QODTA QODTB
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PS8743D
11/06/07
PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer
Pin Configuration 1:2 Register (C0 = 1, C1 = 1)
1 A B C D E F G H J K L M N P R T D1 D2 D3 D4 D5 D6 NC CK CK D8 D9 D10 DODT D12 D13 DCKE 2 NC NC NC NC NC NC RST DCS CSR NC NC NC NC NC NC NC 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 5 Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA ZOH Q8A Q9A Q10A Q12A Q13A 6 Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB ZOL Q8B Q9B Q10B Q12B Q13B
QODTA QODTB
QCKEA QCKEB
NB, 96-ball LFBGA (MO-205CC)
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PS8743D
11/06/07
PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer
Terminal Functions
Name GND VDD VREF ZOH ZOL CK CK C0, C1 RST CSR, DCS D1, D25 DODT DCKE Q1-Q25 QCS QODT QCKE Ground Power Supply Input Reference Voltage Reserved for future use Reserved for future use Positive master clock input Negative master clock input Configuration control inputs Asynchronous reset input - resets registers and disables VREF data and clock differential - input receivers Chip select inputs disables D1-D24 outputs switching when both inputs are high Data input - clocked in on the crossing of the rising edge of CK and the falling edge of CK The outputs of this register bit will not be suspended by the DCS and CSR control The outputs of this register bit will not be suspended by the DCS and CSR control Data outputs that are suspended by the DCS and CSR control Data output that will not be suspended by the DCS and CSR controll Data output that will not be suspended by the DCS and CSR controll Data output that will not be suspended by the DCS and CSR controll Description Characteristics Ground Input 1.8V nominal 0.9V nominal Input Input Differential Clock input Differential Clock input LVCMOS inputs LVCMOS inputs SSTL_18 input SSTL_18 input SSTL_18 input SSTL_18 input 1.8V CMOS 1.8V CMOS 1.8V CMOS 1.8V CMOS
Function Table (each flip-flop)
Inputs RST H H H H H H H H H H H H L DCS L L L L L L H H H H H H CSR L L L H H H L L L H H H CK L or H L or H L or H L or H CK L or H L or H L or H L or H Dn, DODT, DCKE L H X L H X L H X L H X Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs QCS L L Q0 L L Q0 H H Q0 H H Q0 L QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L
X or floating X or floating X or floating X or floating X or floating
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PS8743D
11/06/07
PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................................... -65C to +150C Supply Voltage Range, VDD .............................................-0.5V to 2.5V Input Voltage Range,VI : (See Notes 2 and 3): ................-0.5V to 2.5V Output Voltage Range, VO (See Notes 2 and 3) .... -0.5V to VDD + 0.5V Input Clamp Current, IIK (VI < 0 or VI = VDD ) .........................-50mA Output Clamp Current, IOK (VO < 0 or VO > VDD) ................... 50mA Continous Output Current, IO (VO = 0 to VDD) ........................ 50mA Continous Current through each VDD or GND ......................... 100mA
Notes: 1. Stresses greater than those listed under MAXIMUM RAINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 2.5V maximum
Recommended Operating Conditions(1)
Parameters VDD VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VID IOH IOL TA Supply Voltage Reference Voltage Termination Voltage Input Voltage AC High - Level Input Voltage AC Low- Level Input Voltage DC High - Level Input Voltage DC Low- Level Input Voltage High Level Input Voltage Low Level Input Voltage Common-mode input Voltage Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-air Temperature 0 RST, CN CK, CK 0.65 x VDD 0.35 x VDD 0.675 600 -8 -8 70 1.125 mV mA C Data Inputs Description Min. 1.7 0.49 x VDD VREF -40mA 0 VREF +250mV VREF -250mV VREF +125mV VREF -125mV V 0.50 x VDD VREF Nom. Max. 1.9 0.51 x VDD VREF +40mA VDD Units
Notes: 1. The RST and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating, unless RST is low.
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PS8743D
11/06/07
PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer Electrical Characteristics Over Recommended Operating Free Air Temperature range
Parameters VOH VOL II IDD All inputs Static Stand-by Static Operating Dynamic Operating Clock only Description IOH = -6 mA IOL = 6 mA VI = VDD or GND RST = GND RST = VDD, VI = VIH(AC) or VIL(AC) RST = VDD, VI = VIH(AC), or VIL(AC) CK and CK switching 50% duty cycle IO = 0 1.8V 28 1.9V Test Conditions VDD 1.7V 1.7V Min. 1.2 0.5 5 100 40 A mA A/ clock MHz Nom. Max. Units V
IDDD
RST = VDD, VI = VIH(AC), or VIL(AC) CK and CK switching 50% Dynamic Operating - per duty cycle. One data input switcheach data input, 1:1 mode ing at half clock frequency, 50% duty cycle RST = VDD, VI = VIH(AC), or VIL(AC) CK and CK switching 50% Dynamic Operating - per duty cycle. One data input switcheach data input, 1:2 mode ing at half clock frequency, 50% duty cycle Data inputs VI = VREF 250mV VICR = 0.9V, VID = 600mV VI = VDD or GND
36
36
A/ clock MHz data input
2.5 2 2.5
3.5 3 pF
CI
CK and CK RST
Timing Requirements Over Recommended Operating Free Air Temperature range (See Figure 1)
Parameter fclock tW tact(1) tinact(1) tsu th Clock frequency Pulse Duration, CK, CK, High or low Differential inputs active time(1) time(2) 0.7 0.5 0.5 0.5 DCS before CK, CK, CSR high Setup time Hold Time DCS before CK, CK, CSR low ODT, CKE and data before CK, CK DCS, ODT, CKE and data before CK, CK Differential inputs inactive 1 10 15 ns Description Min. Max 350 Units MHz
Notes: 1. This parameter is not necessarily production tested. 2. Data and VREF inputs must be a low minimum time of tact max, after RST is taken high. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max after RST is taken low.
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PS8743D
11/06/07
PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer
Switching Characteristics (Over Recommended Operating Free Air Temperature range)
Parameter fmax tpdm tpdmss (simultaneous switching)(1,2) tRPHL From CK and CK CK and CK To (see Fig. 1) "Test Point" "Test Point" Min. 1.2 Max. 350 1.90 2.00 Units MHz ns ns
RST
Q
0
3
ns
Notes: 1. Includes 350ps test load transmission-line delay. 2. This parameter is not necessarily production tested.
Output Edge Rates Over Recommended Operating Free Air Temperature range (See Figure 2)
Parameter dV/dt_r dV/dt_f dV/dt(1) VDD = 1.8V 0.1V Min. 1 1 Max. 4 4 1 V/ns Units
Notes: 1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
07-0266
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PS8743D
11/06/07
PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer
Test Circuit and Switching Waveforms
VDD DUT TL= 50-ohm CK Inputs Test Point RL= 100-ohm Test Point CK Out CK TL= 350ps, 50-ohm Test Point R = 1000-ohm CL= 30pF (see note 1) R = 1000-ohm
Load Circuit
CK VICR CK t PLH
90% 10%
LVCMOS RST Input
VDD VDD/2 VDD/2 0V
VICR t PHL
VID
t inact
IDD(2)
tact
Output
VOH VOL
VTT
VTT
Voltage and Current Waveforms Input Active and Inactive Times
Voltage Waveforms - Propagation Delay Times
tw
Input VICR VICR VID
LVCMOS RESET Input VIH VDD/2 VIL
tRPHL
Voltage Waveforms - Pulse Duration
Output
VOH VTT VOL
Voltage Waveforms - Propagation Delay Times
CK VICR CK tsu VREF Input th VIH VREF VIL VID
Voltage Waveforms - Setup and Hold Times
Figure 1. Parameter Measurement Information (VDD = 1.8V 0.1V)
Notes: 1. CL includes probe and jig capacitance 2. IDD tested with clock and data inputs held at VDD or GND and IO = 0mA 3. All input pulses are supplied by generators having the following characteristics: Pulse Repertition Rate 10 MHz, ZO = 50, input slew rate = 1V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VREF = VDD /2 6. VIH = VREF +250mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF -250mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV 9. tPLH and tPHL are the same as tpdm.
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PS8743D
11/06/07
PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer
VDD DUT R = 50-ohm Out CL= 10pF (see note 1) Test Point
Load Circuit -High -to- Low Slew Rate Measurement
Output
dv_f 80% 20% dt_f VOH
VOL
Voltage Waveforms - High -to- Low Slew Rate Measurement
DUT Out CL= 10pF (see note 1) Test Point RL = 50-ohm
Load Circuit - Low -to- High Slew Rate Measurement
dv_r dv_r 80% Output 20% VOH VOL
Voltage Waveforms - Low -to- High Slew Rate Measurement
Figure 2. Output Slew-Rate Measurement Information (VDD = 1.8V 0.1V)
Notes: 1. CL includes probe and jig capacitance 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified).
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PS8743D
11/06/07
PI74SSTUA32864 25-Bit 1:1, or 14-Bit 1:2 Configurable Registered Buffer
Packaging Mechanical: 96-ball LFBGA (NB)
DATE: 09/11/06
Notes:
DESCRIPTION: 96-ball, Low Profile Fine Pitch Ball Grid Array (LFBGA) PACKAGE CODE: NB96 DOCUMENT CONTROL #: PD-2004 REVISION: C
1. 2.
Controlling dimensions in millimeters Ref: JEDEC MO-205F/CC
06-0735
Ordering Information
Ordering Code PI74SSTUA32864NB PI74SSTUA32864NBE Package Code NB NB Package Description 96-Ball LFBGA Pb-free & Green, 96-Ball LFBGA
Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. Number of Transistors = TBD
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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PS8743D
11/06/07

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